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Std_Logic_1164Std_logic_1164 is a VHDL package in the library IEEE. It is the IEEE standard for describing digital logic values in VHDL. It defines type Std_logic to represent a single bit of digital information, and Std_logic_vector to represent a bus. It also contains VHDL functions for these types to resolve tristate bus conflicts, functions to define logical operators, and conversions functions to and from other standard data types. Significantly, it does not contain any arithmetic or comparison operators, or any conversion functions to and from integer types. These are usually found in packages from synthesis tool vendors, or in the new IEEE 1076.3 standard package NUMERIC_STD.
VHDL Source Of Package
package Std_logic_1164 is
type Std_ulogic is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-'); -- Don't care
type Std_ulogic_vector is
array (NATURAL range <>) of Std_ulogic;
function Resolved (S: Std_ulogic_vector)
return Std_ulogic;
subtype Std_logic is Resolved Std_ulogic;
type Std_logic_vector is
array (NATURAL range <>) of Std_logic;
subtype X01 is Resolved Std_ulogic range 'X' to '1';
subtype X01Z is Resolved Std_ulogic range 'X' to 'Z';
subtype UX01 is Resolved Std_ulogic range 'U' to '1';
subtype UX01Z is Resolved Std_ulogic range 'U' to 'Z';
function "and" (L, R: Std_ulogic) return UX01;
function "nand" (L, R: Std_ulogic) return UX01;
function "or" (L, R: Std_ulogic) return UX01;
function "nor" (L, R: Std_ulogic) return UX01;
function "xor" (L, R: Std_ulogic) return UX01;
function "xnor" (L, R: Std_ulogic) return UX01;
function "not" (L: Std_ulogic) return UX01;
function "and" (L, R: Std_logic_vector)
return Std_logic_vector;
function "and" (L, R: Std_ulogic_vector)
return Std_ulogic_vector;
function "nand" (L, R: Std_logic_vector)
return Std_logic_vector;
function "nand" (L, R: Std_ulogic_vector)
return Std_ulogic_vector;
function "or" (L, R: Std_logic_vector)
return Std_logic_vector;
function "or" (L, R: Std_ulogic_vector)
return Std_ulogic_vector;
function "nor" (L, R: Std_logic_vector)
return Std_logic_vector;
function "nor" (L, R: Std_ulogic_vector)
return Std_ulogic_vector;
function "xor" (L, R: Std_logic_vector)
return Std_logic_vector;
function "xor" (L, R: Std_ulogic_vector)
return Std_ulogic_vector;
function "xnor" (L, R: Std_logic_vector)
return Std_logic_vector;
function "xnor" (L, R: Std_ulogic_vector)
return Std_ulogic_vector;
function "not" (L: Std_logic_vector)
return Std_logic_vector;
function "not" (L: Std_ulogic_vector)
return Std_ulogic_vector;
function To_Bit (S: Std_ulogic; Xmap: BIT := '0')
return BIT;
function To_Bitvector (S: Std_logic_vector;
Xmap: BIT:='0')
return BIT_VECTOR;
function To_Bitvector (S: Std_ulogic_vector;
Xmap: BIT:='0')
return BIT_VECTOR;
function To_StdULogic (B: BIT)
return Std_ulogic;
function To_StdLogicVector (B: BIT_VECTOR)
return Std_logic_vector;
function To_StdLogicVector (S: Std_ulogic_vector)
return Std_logic_vector;
function To_StdULogicVector(B: BIT_VECTOR)
return Std_ulogic_vector;
function To_StdULogicVector(S: Std_logic_vector)
return Std_ulogic_vector;
function To_X01 (S: Std_logic_vector)
return Std_logic_vector;
function To_X01 (S: Std_ulogic_vector)
return Std_ulogic_vector;
function To_X01 (S: Std_ulogic)
return X01;
function To_X01 (B: BIT_VECTOR)
return Std_logic_vector;
function To_X01 (B: BIT_VECTOR)
return Std_ulogic_vector;
function To_X01 (B: BIT)
return X01;
function To_X01Z (S: Std_logic_vector)
return Std_logic_vector;
function To_X01Z (S: Std_ulogic_vector)
return Std_ulogic_vector;
function To_X01Z (S: Std_ulogic)
return X01Z;
function To_X01Z (B: BIT_VECTOR)
return Std_logic_vector;
function To_X01Z (B: BIT_VECTOR)
return Std_ulogic_vector;
function To_X01Z (B: BIT)
return X01Z;
function To_UX01 (S: Std_logic_vector)
return Std_logic_vector;
function To_UX01 (S: Std_ulogic_vector)
return Std_ulogic_vector;
function To_UX01 (S: Std_ulogic)
return UX01;
function To_UX01 (B: BIT_VECTOR)
return Std_logic_vector;
function To_UX01 (B: BIT_VECTOR)
return Std_ulogic_vector;
function To_UX01 (B: BIT)
return UX01;
function Rising_edge (signal S: Std_ulogic)
return BOOLEAN;
function Falling_edge (signal S: Std_ulogic)
return BOOLEAN;
function Is_X (S: Std_ulogic_vector) return BOOLEAN;
function Is_X (S: Std_logic_vector) return BOOLEAN;
function Is_X (S: Std_ulogic) return BOOLEAN;
end Std_logic_1164;
Things to rememberRising_edge and Falling_edge are the best way to detect clock edges, but not all synthesis tools support these functions!The alternative to Rising_edge(Clock) is to use the expression:
Clock'EVENT and Clock = '1'
The don't care value '-' is intended to be used as an output don't care, not an input don't care. A comparison like A = '-' will be false unless A is literally '-' !
TipsThe IEEE standard data types are Std_logic and Std_logic_vector, which are resolved subtypes, so can be used for signals with more than one driver (i.e. tristate busses). The types Std_ulogic and Std_ulogic_vector are unresolved types, so signals with these types can have only one driver. It is a good idea to use types Std_ulogic and Std_ulogic_vector for signals that are intended to have just one driver (i.e. most signals in a design!), since if two outputs are inadvertently wired together, this will be immediately reported as an error by the simulator. However, Std_ulogic and Std_ulogic_vector are not the standard types, so their use might not be supported by some tools.See AlsoStandard, Numeric_std, Package |
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